Constant-time software
For SQUIP, the vendor’s guidance is constant-time software. There is no microcode fix. Every sensitive path becomes a rewrite tax across the stack.
Secure Simultaneous Multi-Threading
Both hardware threads keep running. The side channel closes.
SSMT is a hardware-level fix for the execution-contention side channels that simultaneous multi-threading opens. Both threads stay on. Neither parks the sibling, and you do not rewrite every workload in constant time.
Performance figures on this page are reported by the inventor’s bench. Commercial access is a mutual NDA, then a synchronized 30-day technical data room for Tier-1 buyers.
Thread A
Running
Thread B
Running
One core. Two workers. A wall between them. Neither strands the other.
The problem
SMT shares a core. That sharing leaks.
Simultaneous multi-threading puts two hardware threads on one physical core so they share execution ports and scheduler queues. That is how modern servers get more work from the same silicon, and how a co-located process or VM can measure contention and recover secrets.
The published class includes port contention (SMoTherSpectre, 2019) and scheduler-queue contention (SQUIP, Gast et al., IEEE S&P 2023). On AMD, the SQUIP exemplar reaches Zen 1 through Zen 4 with SMT enabled (AMD-SB-1039; CVE-2021-46778).
Sources: Aldaya et al. 2019; Gast et al., IEEE S&P 2023; AMD product security bulletin, Dec 2023.
Sibling isolation
Newer SMT Protection lets a guest force its sibling idle. That isolates the guest by stranding the sibling’s concurrency. It does not eliminate the channel for everyone else.
SMT off
Disabling SMT costs roughly 12 to 15% throughput on some EPYC workloads, against SMT gains of 30 to 50% on compute-bound work. Some cloud providers already run with SMT off.
In plain language
The layman explainer
Two workers at one desk. A spy that never trips an alarm. A wall that lets both keep working.
SSMT explainer. Visuals only. Voice-over version coming next.
The fix (claim level)
Keep SMT. Close the channel.
SSMT is a hardware approach that retains simultaneous multi-threading while addressing the contention side channel. On compute-heavy loads, restoring SMT concurrency means recapturing up to roughly half the throughput that SMT-off left on the table. Mechanism details stay under NDA and patent counsel.
Reported by the inventor’s bench. Full artifacts open in the technical data room under NDA.
0.042%
Execution overhead (reported bench point)
Inventor-reported
0.04% to 5%
Of total CPU power, depending on part and configuration
Inventor-reported
100%
Of SMT concurrency retained
Inventor-reported
+0.711 ns
Timing slack at closure on an Amazon FPGA instance
Inventor-reported
TTSim
Verified in full Verilog simulation
Inventor-reported
FPGA
Deployed with timing closure on an Amazon FPGA instance
Inventor-reported
Who it is for
Hyperscalers, CPU vendors, confidential compute
Hyperscaler infrastructure teams
Cloud density at global scale. SMT-off buys safety by giving back capacity. SSMT is the path that aims to keep both, with economics measured in avoided CapEx, power, and real estate.
CPU vendors and silicon architects
A design that keeps SMT on the datasheet without the current workaround tax. The commercial path includes immediate rights to integrate the RTL/IP block into active tape-outs.
Confidential-computing providers
Guests that share a core still share ports and queues. Closing the contention class is part of the trust story your customers buy.
Commercial terms
Thirty days. Production license. Competitive process.
This is not a small paid trial. After a mutual NDA, we open a synchronized 30-day technical data room for Tier-1 buyers. The entry fee is a production license.
-
1
Mutual NDA, then the data room. Technical artifacts and diligence materials open under NDA. No LOI that locks the asset off the market.
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2
$50 million within 30 days. A non-refundable production license and exclusivity fee, wired within 30 days of signing the mutual NDA and opening the technical data room. Silicon architects get immediate rights to integrate the RTL/IP block into active server chip tape-outs.
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3
Transaction value anchored in the billions. Deploying this IP at hyperscaler scale unlocks avoided server CapEx, power, and real estate. The $50M is the toll to enter and secure exclusivity while the definitive valuation and royalty structures are finalized.
Process: competitive. We issue a process letter and take Indications of Interest in parallel. We do not sign an early LOI that takes SSMT off the market for one party. Full term sheets and regulatory sequencing stay under counsel in the data room.
Request accessAbout
Bare AI Labs
SSMT is the first public offering from Bare AI Labs’ compute-efficiency program. More is in the pipeline. We license critical infrastructure IP to parties who can put it in silicon. Inventor-reported figures are labeled as such; the data room is where diligence happens.